1. Field of the Invention
The present invention relates to a semiconductor device having a plurality of MIM capacitors and a method of manufacturing the semiconductor device.
2. Background Art
Japanese Laid-Open Patent Publication No. 2007-250760 discloses a semiconductor device having an MIM capacitor wherein the MIM capacitor is formed of a top wiring layer, a capacitance layer, and a flip-chip pad (F/CPAD).
In order to reduce the size of a semiconductor device having a plurality of MIM capacitors, the semiconductor device is preferably configured in such a manner that some of the MIM capacitors are formed on wiring layers or other MIM capacitors. (Such overlying MIM capacitors are referred to as “upper MIM capacitors.”) The upper electrode of each upper MIM capacitor is preferably formed to have a relatively small width in order to ensure insulation of the upper MIM capacitor from adjacent device structures of the semiconductor device.
However, a reduction in the width of the upper electrode of the upper MIM capacitor results in a reduction in adhesion between the upper electrode and the underlying dielectric film, causing the upper electrode to detach or peel from the dielectric film.
The width of the upper electrode of the upper MIM capacitor may be increased to prevent the upper electrode from detaching or peeling from the underlying dielectric film. However, the dielectric film of the upper MIM capacitor typically has steps associated with the thickness of the wiring layer or MIM capacitor underlying the upper MIM capacitor. This means that in order to increase the width of the upper electrode of the upper MIM capacitor, it is necessary to form the electrode over those steps of the dielectric film. In that case, however, the upper electrode may detach or peel from the steps.